Front-end processing

TDA7703

22/32

Rev 1

4

Front-end processing

All the parameters in this section refer to the programmability of the FE part of the device

(registers). The part of the registers that are not described here have either fixed values or

values written by the tuner drivers, and are described in the proper technical documentation

(Communication Protocol manual).

Table 16.

Register 0x00

Register number

Register definition

MSB

LSB

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

AM AGC mode

0

LNA and PIN diode

1

PIN diode only

AM AGC time constant

0

0

slow (125 ms with 1 µF)

0

1

medium (25 ms with 1 µF)

1

1

fast (5 ms with 1 µF)

AM AGC threshold @ mixin

0

0

0

90 dBµV

0

0

1

91 dBµV

0

1

0

92 dBµV

0

1

1

93 dBµV

1

0

0

90 dBµV

1

0

1

89 dBµV

1

1

0

88 dBµV

1

1

1

87 dBµV

AM AGC attack time constant

0

normal

1

fast