PC87332 datasheet(5/98 Pages) NSC

5 / 98 page

List of Figures

FIGURE 2-1

PC87332VLJPC87332VLJ-5 Configuration Registers

FIGURE 2-2

PC87332 Four Floppy Drive Circuit Example

FIGURE 3-1

FDC Functional Block Diagram

FIGURE 4-1

FDC Command Structure

FIGURE 4-2

IBM Perpendicular and ISO Formats Supported by the Format Command

FIGURE 5-1

PC87332 Dynamic Window Margin Performance

FIGURE 5-2

Read Data AlgorithmState Diagram

FIGURE 5-3

Perpendicular Recording Drive RW Head and Pre-Erase Head

FIGURE 6-1

PC87332 Composite Serial Data

FIGURE 6-2

Reciever FIFO Trigger Level

FIGURE 7-1

EPP 17 Address Write

FIGURE 7-2

EPP 17 Address Read

FIGURE 7-3

EPP Write with ZWS

FIGURE 7-4

EPP 19 Address Write

FIGURE 7-5

EPP 19 Address Read

FIGURE 7-6

ECP (Forward) Write Cycle

FIGURE 7-7

ECP (Backward) Read Cycle

FIGURE 8-1

IDE Interface Signal Equations (Non-DMA)

FIGURE 9-1

Clock Timing

FIGURE 9-2

Microprocessor Read Timing

FIGURE 9-3

Microprocessor Write Timing

FIGURE 9-4

Baud Out Timing

FIGURE 9-5

Transmitter Timing

FIGURE 9-6a

Sample Clock Timing

FIGURE 9-6b

Receiver Timing

FIGURE 9-6c

Mode Receiver Timing

FIGURE 9-6d

Timeout Receiver Timing

FIGURE 9-7

MODEM Control Timing

FIGURE 9-8

DMA Timing

FIGURE 9-9

Reset Timing

FIGURE 9-10

Write Data Timing

FIGURE 9-11

Drive Control Timing

FIGURE 9-12

Read Data Timing

FIGURE 9-13

IDE Timing

FIGURE 9-14

Compatible Mode Parallel Port Interrupt Timing

FIGURE 9-15

Extended Mode Parallel Port Interrupt Timing

FIGURE 9-16

Typical Parallel Port Data Exchange

FIGURE 9-17

Enhanced Parallel Port Timing

FIGURE 9-18

ECP Parallel Port Forward Timing Diagram

FIGURE 9-19

ECP Parallel Port Backward Timing Diagram

PC87332 데이터시트(PDF) 5 Page - National Semiconductor (TI)

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