PC97338 datasheet(40/221 Pages) NSC

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The Linear Feedback Shift Register

(LFSR)

The LFSR is an 8-bit shift register that resets to the

value of 0x6A. (See Figure 2.) The feedback taps for

this shift register are taken from register bits 1 and 0

of LFSR.

The initiation key should be sent to the Chip upon

power on. The software should ensure that the LFSR

is in its initial state. Then 32 writes are performed. The

first 30 writes must be exactly equal to the 30 values

the LFSR will generate starting from 0x6A. The last

two writes are of 0x00.

The exact sequence for the initiation key in hexadec-

imal notation is (reading left to right, top to bottom):

6A, B5, DA, ED, F6, FB, 7D, BE,

DF, 6F, 37, 1B, 0D, 86, C3, 61,

B0, 58, 2C, 16, 8B, 45, A2, D1,

E8, 74, 3A, 9D, CE, E7, 00, 00

FIGURE 2. LFSR Circuit

Relocating the INDEX and DATA Register

Pair

The INDEX and DATA registers are relocated via con-

figuration registers SBAL and SBAH, as follows:

1. Write to the SBAH register.

A temporary register (TEMP_SBAH) is updated

with the written data (as in all configuration regis-

ters). SBAH register is not updated yet with the

written data, i.e., a read from SBAH register will re-

turn the data prior to the write.

The addresses of the INDEX and DATA registers

are not modified.

2. Write to the SBAL register.

The second consecutive write updates the SBAL

SBAH register with the data stored in the tempo-

rary register (TEMP_SBAH).

The addresses of the INDEX and DATA registers

are modified according to the data of SBAL and

SBAH.

3. Return to (1) if addresses of the INDEX and DATA

registers need to be changed again.

Upon reset, TEMP_SBAH is initialized to the initializa-

tion value of the SBAH register. When the SBAH reg-

ister is updated by the Plug and Play protocol,

TEMP_SBAH is updated too, with the same value.

This scheme maintains the coherence of the INDEX

and DATA register addresses.

2.3

THE CONFIGURATION REGISTERS

The next section presents the bitmaps of the configu-

ration registers in address order. The sections that fol-

low describe the bits and fields of each register in

detail, in the same order.

“Reset” specifies the value of a bit after reset. “Re-

quired” indicates that the bit must always have that

value.

To maintain compatibility with other SuperI/O chips,

the value of reserved bits may not be altered. Use

read-modify-write to preserve their values.

Shift Direction

Write to

I/O Port

Reset

Values

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