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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CC1020-RTR1 데이터시트(PDF) 24 Page - Texas Instruments |
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CC1020-RTR1 데이터시트(HTML) 24 Page - Texas Instruments |
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24 / 95 page  xosc f B.R. 8 (REF _ DIV 1) DIV1 DIV2 = ´ + ´ ´ Time 1 0 1 1 0 0 0 1 1 0 1 Tx data Time 1 0 1 1 0 0 0 1 1 0 1 Tx data DCLK is not used in transmit mode, and is used as data output in receive mode. It can be set to default high or low in transmit mode. FSK modulating signal, internal in CC1020 Data provided by UART (TXD) Transmitter side: DCLK is used as data output provided by CC1020. Connect to UART (RXD) Demodulated signal (NRZ), internal in CC1020 DIO is not used in receive mode. Used only as data input in transmit mode DCLK DIO “RF” “RF” DCLK DIO Receiver side: DCLK is not used in transmit mode, and is used as data output in receive mode. It can be set to default high or low in transmit mode. FSK modulating signal, internal in CC1020 Data provided by UART (TXD) Transmitter side: DCLK is used as data output provided by CC1020. Connect to UART (RXD) Demodulated signal (NRZ), internal in CC1020 DIO is not used in receive mode. Used only as data input in transmit mode DCLK DIO “RF” “RF” DCLK DIO Receiver side: CC1020 SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015 www.ti.com Figure 5-8. Transparent Asynchronous UART Mode (SEP_DI_DO = 1) Figure 5-9. Manchester Encoding 5.7 Data Rate Programming The data rate (baud rate) is programmable and depends on the crystal frequency and the programming of the CLOCK (CLOCK_A and CLOCK_B) registers. The baud rate (B.R.) is given by Equation 1. (1) Where: DIV1 and DIV2 are given by the value of MCLK_DIV1 and MCLK_DIV2. Table 5-4 shows some possible data rates as a function of crystal frequency in synchronous mode. In asynchronous transparent UART mode any data rate up to 153.6 kBaud can be used. Table 5-2. DIV2 for Different Settings of MCLK_DIV2 MCLK_DIV2[1:0] DIV2 00 1 01 2 10 4 11 8 24 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC1020 |
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