TNETV2664FIBZWT datasheet(200/249 Pages) TI1

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Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

CLKX

FSX

TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

www.ti.com

Table 6-47. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1(1) (2)

(see Figure 6-29)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MASTER

SLAVE

MIN

MAX

MIN

MAX

tsu(DRV-CKXH)

Setup time, DR valid before CLKX high

2 - 3P

th(CKXH-DRV)

Hold time, DR valid after CLKX high

5 + 6P

(1)

P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10ns.

(2)

For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should

program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.

Table 6-48. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI

Master or Slave: CLKSTP = 10b, CLKXP = 1(1) (2) (see Figure 6-29)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

PARAMETER

UNIT

MASTER(3)

SLAVE

MIN

MAX

MIN

MAX

th(CKXH-FXL)

Hold time, FSX low after CLKX high(4)

T - 4

T + 5.5

td(FXL-CKXL)

Delay time, FSX low to CLKX low(5)

H - 4

H + 4

td(CKXL-DXV)

Delay time, CLKX low to DX valid

-4

5.5

3P + 2.8

5P + 17

Disable time, DX high impedance following

tdis(CKXH-DXHZ)

H - 6

H + 7.5

last data bit from CLKX high

Disable time, DX high impedance following

tdis(FXH-DXHZ)

P + 3

3P + 17

last data bit from FSX high

td(FXL-DXV)

Delay time, FSX low to DX valid

2P + 2

4P + 17

(1)

P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10ns.

(2)

For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should

program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.

(3)

S = Sample rate generator input clock = 2P if CLKSM = 1 (P = SYSCLK3 period)

S = Sample rate generator input clock = 2P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd

(4)

FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input

on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5)

FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

Figure 6-29. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

200

Peripheral Information and Electrical Specifications

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