TNETV2664FIBZWT datasheet(197/249 Pages) TI1

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Bit(n-1)

(n-2)

(n-3)

Bit 0

Bit(n-1)

(n-2)

(n-3)

CLKS

CLKR

FSR (int)

FSR (ext)

CLKX

FSX (int)

FSX (ext)

FSX (XDATDLY=00b)

13(A)

CLKS

FSR external

CLKR/X (no need to resync)

CLKR/X (needs resync)

TMS320C6424

www.ti.com

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

Parameter No. 13 applies to the first data bit only when XDATDLY

≠ 0.

Figure 6-25. McBSP Timing(B)

Table 6-42. Timing Requirements for FSR When GSYNC = 1 (see Figure 6-26)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MIN

MAX

tsu(FRH-CKSH)

Setup time, FSR high before CLKS high

th(CKSH-FRH)

Hold time, FSR high after CLKS high

Figure 6-26. FSR Timing When GSYNC = 1

Table 6-43. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0(1) (2)

(see Figure 6-27)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MASTER

SLAVE

MIN

MAX

MIN

MAX

tsu(DRV-CKXL)

Setup time, DR valid before CLKX low

2 - 3P

(1)

P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10ns.

(2)

For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should

program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.

Peripheral Information and Electrical Specifications

197

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