 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
TNETV2664FIBZWT 데이터시트(PDF) 220 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TNETV2664FIBZWT 데이터시트(HTML) 220 Page - Texas Instruments |
|
|
220 / 249 page  1 4 5 MDCLK MDIO (input) 3 3 1 7 MDCLK MDIO (output) TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com 6.16.2 Management Data Input/Output (MDIO) Electrical Data/Timing Table 6-67. Timing Requirements for MDIO Input (see Figure 6-41 and Figure 6-42) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT MIN MAX 1 tc(MDCLK) Cycle time, MDCLK 400 ns 2 tw(MDCLK) Pulse duration, MDCLK high/low 180 ns 3 tt(MDCLK) Transition time, MDCLK 5 ns 4 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high 10 ns 5 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high 10 ns Figure 6-41. MDIO Input Timing Table 6-68. Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see Figure 6-42) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT MIN MAX 7 td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid 100 ns Figure 6-42. MDIO Output Timing 220 Peripheral Information and Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
