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TNETV2664FIBZWT 데이터시트(PDF) 232 Page - Texas Instruments

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부품명 TNETV2664FIBZWT
상세설명  Fixed-Point Digital Signal Processor
PDF  249 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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TNETV2664FIBZWT 데이터시트(HTML) 232 Page - Texas Instruments

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VLYNQ_CLK
3
1
2
TMS320C6424
SPRS347D – MARCH 2007 – REVISED DECEMBER 2009
www.ti.com
6.20.2 VLYNQ Electrical Data/Timing
Table 6-83. Timing Requirements for VLYNQ_CLK Input (see Figure 6-45)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
UNIT
MIN
MAX
1
tc(VCLK)
Cycle time, VLYNQ_CLK
10
ns
2
tw(VCLKH)
Pulse duration, VLYNQ_CLK high
3
ns
3
tw(VCLKL)
Pulse duration, VLYNQ_CLK low
3
ns
Table 6-84. Switching Characteristics Over Recommended Operating Conditions for VLYNQ_CLK Output
(see Figure 6-45)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
PARAMETER
UNIT
MIN
MAX
1
tc(VCLK)
Cycle time, VLYNQ_CLK
10
ns
2
tw(VCLKH)
Pulse duration, VLYNQ_CLK high
4
ns
3
tw(VCLKL)
Pulse duration, VLYNQ_CLK low
4
ns
Figure 6-45. VLYNQ_CLK Timing for VLYNQ
Table 6-85. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the
VLYNQ Module (see Figure 6-46)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
PARAMETER
UNIT
MIN
MAX
td(VCLKH-
1
Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] invalid
2.25
ns
TXDI)
td(VCLKH-
2
Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] valid
12
ns
TXDV)
232
Peripheral Information and Electrical Specifications
Copyright © 2007–2009, Texas Instruments Incorporated
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Product Folder Link(s): TMS320C6424



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