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STBC02BJR 데이터시트(PDF) 8 Page - STMicroelectronics |
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STBC02BJR 데이터시트(HTML) 8 Page - STMicroelectronics |
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8 / 39 page ![]() Pin configuration (top through view) STBC02 8/39 DocID029261 Rev 2 2 Pin configuration (top through view) Figure 2: Pin configuration top through view Table 2: Pin description Bump Bump name Description Power IN E5-F5 Input supply voltage. Bypass this pin to ground with a 10 µF capacitor BAT A5-B5 Battery positive terminal. Bypass this pin to GND with a 4.7 µF ceramic capacitor SYS C5-D5 System output. Bypass this pin to ground with 1 µF ceramic capacitor LDO F4 LDO output. Bypass this pin to ground with 1 µF ceramic capacitor NTC D1 Battery temperature monitor pin AGND B4 Analog ground Connect together with the same ground layer GND A3 GROUND Programming ISET A4 Fast charge current programming resistor IPRE D4 Pre-charge current programming resistor Sensing BATMS C4 Battery voltage measurement pin BATSNS B3 Battery voltage sensing. Connect as close as possible to the battery positive terminal BATSNSFV A2 Floating voltage sensing. Connect as close as possible to the battery positive terminal Digital I/Os CEN B1 Charger enable pin. Active high. 500 kΩ internal pull-up (to LDO) CHG E1 Charging/fault flag. Active low (open drain output) WAKE-UP D2 Shipping mode exit input pin. Active high. 50 kΩ internal pull-down SW_SEL C1 Load switch selection input (refer to LDO level) |
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