TNETV2685FIBZUT5 datasheet(70/191 Pages) TI1

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CLKIN

TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

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6.5.2

PLL2 Controller Operating Modes

Unlike the PLL1 controller that can operate in bypass and a PLL mode, the PLL2 controller only operates

in PLL mode. PLL2 is unlocked only during the power-up sequence (see Section 6.7) and is locked by the

time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

6.5.3

PLL2 Controller Input Clock Electrical Data/Timing

Table 6-11. Timing Requirements for CLKIN2(1) (2) (see Figure 6-8)

720, 800, 900, 1100

NO.

PLL MODE x20

UNIT

MIN

MAX

tc(CLKIN2)

Cycle time, CLKIN2

37.5

tw(CLKIN2H)

Pulse duration, CLKIN2 high

0.4C

tw(CLKIN2L)

Pulse duration, CLKIN2 low

0.4C

tt(CLKIN2)

Transition time, CLKIN2

1.2

tJ(CLKIN2)

Period jitter, (peak-to-peak) CLKIN2

100

(1)

The reference points for the rise and fall transitions are measured at 3.3-V VIL MAX and VIH MIN.

(2)

C = CLKIN2 cycle time in ns. For example, when CLKIN2 frequency is 25 MHz, use C = 40 ns.

Figure 6-8. CLKIN2 Timing

6.5.4

PLL2 Controller Register Description(s)

A summary of the PLL2 controller registers is shown in Table 6-12.

Table 6-12. PLL2 and Reset Controller Registers Memory Map

HEX ADDRESS RANGE

DESCRIPTION

0x0212 0000

PID

Peripheral Identification and Revision Information Register

0x0212 0100

PLLCTL

PLL Controller 2 Operations Control Register

0x0212 0110

PLLM

PLL Controller 2 Multiplier Control Register

0x0212 0138

PLLCMD

PLL Controller 2 Command Register

0x0212 013C

PLLSTAT

PLL Controller 2 Status Register (Shows PLLC1 Status)

Peripheral Information and Electrical Specifications

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Product Folder Link(s): TMS320DM647 TMS320DM648

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