TMS320VC5470GHKA datasheet(21/93 Pages) TI

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DSP Subsystem Functional Overview

December 2001 – Revised December 2002

SPRS017B

DSP Subsystem Functional Overview

The DSP subsystem is based on the TMS320C54x DSP core, on-chip memories and peripherals, and is

code-compatible with other C54x products. The following description of the 5470 DSP subsystem is based

on Figure 3–1.

8 K

× 16

Prog RAM

8 K

× 16

Prog RAM

8 K

× 16

Prog RAM

8 K

× 16

Prog RAM

C54x

 DSP

DMA

McBSP

TIMER

McBSP

8 K

× 16

Data RAM

8 K

× 16

Prog RAM

API

PLL

XIO

External

DSP

Memory

CODEC

DSP Subsystem

8 K

× 16

Data RAM

8 K

× 16

Data RAM

8 K

× 16

Data RAM

MCU Subsystem

Figure 3–1. 5470 DSP Subsystem Functional Block Diagram

3.1

DSP Core

The 5470 DSP subsystem’s fixed-point, digital signal processor (DSP) is based on an advanced modified

Harvard architecture that has one program memory bus and three data memory buses. This processor

provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic,

on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this

DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing

the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.

Instructions with parallel store and application-specific instructions can fully utilize this architecture. In

addition, data can be transferred between data and program spaces. Such parallelism supports a powerful

set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle.

In addition, the 5470 DSP subsystem includes the control mechanisms to manage repeated operations,

function calls, and DSP interrupts.

The DSP core includes the following features:

•

Low-power C54x

 DSP CPU, operating at up to 100 MHz

•

Software-programmable wait-state generator with bank-switching wait-state logic

•

External memory interface

–

Program space

–

Data space

–

I/O space

•

Scan-based emulation logic

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