G.726. At power up, the outputs TSO and RSO are in

TRI-STATE mode. This “cold” reset process is asynchronous

and takes approximately 2000 CLK cycles for the initializa-

tion. During the reset process, the outputs TSO and RSO are

in TRI-STATE mode.

CHANNEL NOP

Each channel can be independently disabled. When EN is at

logic low on the falling edge of CE, the ADPCM transcoder

processing for that channel is disabled. The processor re-

quires 4 CLK cycles for CE to maintain all channel variables.

The data output ports are also placed in known states. After

this the processor waits for the next interrupt. Power is con-

served during this time by disabling the internal registers.

TSO outputs the following data after a channel NOP:

TABLE 6. TSO at Channel NOP

QSEL1

QSEL0

Mode

TSO

0

0

32 kbps

0000

0

1

24 kbps

0000

1

0

16 kbps

0000

1

1

40 kbps

00000

The data pattern at TSO in

Table 6 are shown with 3 ASCK

rising edges within the CE high pulse for the 32, 24, 16 kbps

modes and 4 ASCK rising edges within the CE high pulse for

the 40 kbps mode (the MSB is shifted out with the falling

edge of CE). In the idle case (NOP) where EN is low at the

falling edge of CE, the TSO output is low for the duration of

the high CE pulse.

In the idle state (NOP), RSO outputs the following data (bit

representation with the sign-bit on the left followed by the

MSB, the sign-bit is the first bit after the rising edge of CE):

TABLE 7. RSO at Channel NOP

PCM1

Mode

RSO

0

8-Bit µ-Law

11111111

1

8-Bit A-Law

11010101

9

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