LNBH25LSPQR datasheet(21/30 Pages) STMICROELECTRONICS

21 / 30 page

LNBH25LS

I²C interface protocol

DocID026753 Rev 3

21/30

All bits reset to 0 at power-on

Table 9: Data 4 (read/write register. Register address = 0X5)

Bit

Name

Value

Description

Bit 0

(LSB)

N/A

Reserved. Keep to “0”

Bit 1

N/A

Reserved. Keep to “0”

Bit 2

N/A

Reserved. Keep to “0”

Bit 3

OLR

In case overload protection activation (OLF=1), all VSEL 1..4 bits

are reset to “0” and LNB output (VOUT pin) is disabled. The VSEL

bit must be set again by the master after the overcurrent condition

is removed (OLF=0)

In case of overload protection activation (OLF=1) the LNB output

(VOUT pin) is automatically enabled as soon as the overload

condition is removed (OLF=0) with the previous VSEL bits setting

Bit 4

N/A

Reserved. Keep to “0”

Bit 5

N/A

Reserved. Keep to “0”

Bit 6

THERM

If thermal protection is activated (OTF=1), all VSEL 1..4 bits are

reset to “0” and LNB output (VOUT pin) is disabled. The VSEL bit

must be set again by the master after the overtemperature

condition is removed (OTF=0)

In case of thermal protection activation (OTF=1) the LNB output

(VOUT pin) is automatically enabled as soon as the

overtemperature condition is removed (OTF=0) with the previous

VSEL bits setting

Bit 7

(MSB)

COMP

DC-DC converter compensation: set to use very low E.S.R.

capacitors or ceramic caps on VUP pin

DC-DC converter compensation: set to use standard electrolytic

capacitors on VUP pin

N/A = reserved bit

All bits reset to 0 at power-on

LNBH25LSPQR 데이터시트(PDF) 21 Page - STMicroelectronics

LNBH25LSPQR 데이터시트(HTML) 21 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

데이터시트 다운로드

링크 URL