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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LQFP100 데이터시트(PDF) 16 Page - STMicroelectronics |
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LQFP100 데이터시트(HTML) 16 Page - STMicroelectronics |
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16 / 133 page  Package pinouts and signal descriptions SPC560B54x/6x 16/133 DocID15131 Rev 9 3.2 Pad configuration during reset phases All pads have a fixed configuration under reset. During the power-up phase, all pads are forced to tristate. After power-up phase, all pads are tristate with the following exceptions: PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash. PA[8], PC[0] and PH[9:10] are in input weak pull-up when out of reset. RESET pad is driven low by the device till 40 FIRC clock cycles after phase2 completion. Minimum phase3 duration is 40 FIRC cycles. Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A PC[8] PC[13] PH[15] PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[15] PH[11] NC NC A B PC[9] PB[2] PH[13] PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] PI[2] PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B C PC[14] VDD_H V PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] PI[3] PA[5] PI[5] PE[14] PE[12] PA[9] PA[8] C D PH[14] PI[6] PC[15] PI[7] PH[6] PE[4] PE[2] VDD_L V VDD_H V NC PA[6] PH[12] PG[10] PF[14] PE[13] PA[7] D E PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15] VDD_H V E F PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F G PE[9] PE[8] PE[10] PA[0] VSS_H V VSS_H V VSS_H V VSS_H V VDD_H V PI[12] PI[13] MSEO G H VSS_HV PE[11] VDD_H V NC VSS_H V VSS_H V VSS_H V VSS_H V MDO3 MDO2 MDO0 MDO1 H J RESET VSS_LV NC NC VSS_H V VSS_H V VSS_H V VSS_H V PI[8] PI[9] PI[10] PI[11] J K EVTI NC VDD_B V VDD_L V VSS_H V VSS_H V VSS_H V VSS_H V VDD_H V_ADC 1 PG[12] PA[3] PG[13] K L PG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14] L M PG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12] M N PB[1] PF[9] PB[0] VDD_H V PJ[0] PA[4] VSS_LV EXTAL VDD_H V PF[0] PF[4] VSS_H V_ADC 1 PB[11] PD[10] PD[9] PD[11] N P PF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[14] VDD_L V XTAL PB[10] PF[1] PF[5] PD[0] PD[3] VDD_H V_ADC 0 PB[6] PB[7] P R PF[12] PC[6] PF[10] PF[11] VDD_H V PA[15] PA[13] PI[14] XTAL32 PF[3] PF[7] PD[2] PD[4] PD[7] VSS_H V_ADC 0 PB[5] R T NC NC NC MCKO NC PF[13] PA[12] PI[15] EXTAL 32 PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NOTE: The LBGA208 is available only as development package for Nexus 2+. NC = Not connected Figure 5. LBGA208 configuration |
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