SPC564A70L7 datasheet(13/133 Pages) STMICROELECTRONICS

13 / 133 page

SPC564A70B4, SPC564A70L7

Introduction

Doc ID 18078 Rev 4

13/133

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150 MHz e200z4 Power Architecture® core

–

Variable length instruction encoding (VLE)

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Superscalar architecture with 2 execution units

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Up to 2 integer or floating point instructions per cycle

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Up to 4 multiply and accumulate operations per cycle

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Memory organization

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2 MB on-chip flash memory with ECC and read-while-write (RWW)

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128 KB on-chip SRAM with standby functionality (32 KB) and ECC

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8 KB instruction cache (with line locking), configurable as 2- or 4-way

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14 + 3 KB eTPU code and data RAM

–4

× 4 crossbar switch (XBAR)

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24-entry MMU

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Fail Safe Protection

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16-entry Memory Protection Unit (MPU)

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CRC unit with 3 submodules

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Junction temperature sensor

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Interrupt

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Configurable interrupt controller (INTC) with non-maskable interrupt (NMI)

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64-channel eDMA

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Serial channels

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3 eSCI modules

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3 DSPI modules (2 of which support downstream Micro Second Channel [MSC])

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3 FlexCAN modules with 64 message buffers each

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1 FlexRay module (V2.1) up to 10 Mbit/s w/dual or single channel, 128 message

objects, ECC

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1 eMIOS

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24 unified channels

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1 eTPU2 (second generation eTPU)

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32 standard channels

Reaction Module (REACM)

Works in conjunction with the eQADC and eTPU2 to increase system

performance by removing the CPU from the current control loop.

System Integration Unit (SIU)

Controls MCU reset configuration, pad configuration, external

interrupt, general purpose I/O (GPIO), internal peripheral

multiplexing, and the system reset operation.

Static random-access memory (SRAM)

Provides storage for program code, constants, and variables

System timers

Includes periodic interrupt timer with real-time interrupt; output

compare timer and system watchdog timer

System watchdog timer (SWT)

Provides protection from runaway code

Temperature sensor

Provides the temperature of the device as an analog value

Table 3.

SPC564A70 series block summary (continued)

Block

Function

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