ST7MC1K2-Auto datasheet(59/371 Pages) STMICROELECTRONICS

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Interrupts

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Interrupts

7.1

Introduction

The ST7 enhanced interrupt management provides the following features:

●

Hardware interrupts

●

Software interrupt (TRAP)

●

Nested or concurrent interrupt management with flexible interrupt priority and level

management:

–

up to 4 software programmable nesting levels

–

up to 16 interrupt vectors fixed by hardware

–

2 non maskable events: RESET, TRAP

–

1 maskable top level event: MCES

This interrupt management is based on:

●

bit 5 and bit 3 of the CPU CC register (I1:0),

●

interrupt software priority registers (ISPRx),

●

fixed interrupt vector addresses located at the high addresses of the memory map

(FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard

(not nested) ST7 interrupt controller.

7.2

Masking and processing flow

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx

registers which give the interrupt software priority level of each interrupt vector (see

Table 16). The processing flow is shown in Figure 16.

When an interrupt request has to be serviced:

●

Normal processing is suspended at the end of the current instruction execution.

●

The PC, X, A and CC registers are saved onto the stack.

●

I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx

registers of the serviced interrupt vector.

●

The PC is then loaded with the interrupt vector of the interrupt to service and the first

instruction of the interrupt service routine is fetched (refer to Table 22: Interrupt

mapping for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the

contents of the saved registers to be recovered from the stack.

Note:

As a consequence of the IRET instruction, the I1 and I0 bits are restored from the stack and

the program in the previous level is resumed.

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