STM32F358XC datasheet(14/134 Pages) STMICROELECTRONICS

14 / 134 page

Functional overview

STM32F358xC

14/134

DocID025540 Rev 4

3.7

Power management

3.7.1

Power supply schemes

•

VSS, VDD = 1.8 V+/- 8%: external power supply for I/Os and core. It is provided

externally through VDD pins.

•

VSSA, VDDA = 1.65 to 3.6 V: external analog power supply for ADC, DACs, comparators

operational amplifiers, reset blocks, RCs and PLL. The minimum voltage to be applied

to VDDA differs from one analog peripheral to another. Table 3 provides the summary of

the VDDA ranges for analog peripherals. The VDDA voltage level must be always

greater or equal to the VDD voltage level and must be provided first.

•

VBAT= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch which is guaranteed in the full range of VDD) when

VDD is not present.

3.7.2

Power supply supervision

The device power on reset is controlled through the external NPOR pin. The device remains

in reset state when NPOR pin is held low.

To guarantee a proper power-on reset, the NPOR pin must be held low when VDDA is

applied. Then, when VDD is stable, the reset state can be exited by:

•

either putting the NPOR pin in high impedance. NPOR pin has an internal pull up.

•

or forcing the pin to high level by connecting it to VDDA.

3.7.3

Low-power modes

The STM32F358xC devices support two low-power modes to achieve the best compromise

between low-power consumption, short startup time and available wakeup sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the RTC alarm, COMPx, I2Cx or U(S)ARTx.

Note:

The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop

mode.

Table 3. External analog supply values for analog peripherals

Analog peripheral

Minimum

VDDA supply

Maximum

VDDA supply

ADC

1.8 V

3.6 V

COMP

1.65 V

3.6 V

DAC / OPAMP

2.4 V

3.6V

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