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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32F401CDU6 데이터시트(PDF) 111 Page - STMicroelectronics |
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STM32F401CDU6 데이터시트(HTML) 111 Page - STMicroelectronics |
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111 / 135 page  DocID025644 Rev 3 111/135 STM32F401xD STM32F401xE Electrical characteristics 114 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 42 or Figure 43, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. Figure 43. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. V REF+ STM32F V DDA V SSA/V REF- 1 µF // 10 nF 1 µF // 10 nF ai17535 (See note 1) (See note 1) |
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