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STM32L162VC-A 데이터시트(PDF) 98 Page - STMicroelectronics

부품명 STM32L162VC-A
상세설명  AES-128 bit encryption hardware accelerator
PDF  128 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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STM32L162VC-A 데이터시트(HTML) 98 Page - STMicroelectronics

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Electrical characteristics
STM32L162xC/C-A
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DocID026175 Rev 4
I2S characteristics
Note:
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
trfm
Rise/ fall time matching
tr/tf
90
110
%
VCRS
Output signal crossover voltage
1.3
2.0
V
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
Table 53. I2S characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main Clock Output
256 x 8K 256xFs (1)
1. The maximum for 256xFs is 8 MHz
MHz
fCK
I2S clock frequency
Master data: 32 bits
-
64xFs
MHz
Slave data: 32 bits
-
64xFs
DCK
I2S clock frequency duty cycle Slave receiver, 48KHz
30
70
%
tr(CK)
I2S clock rise time
Capacitive load CL=30pF
-
8
ns
tf(CK)
I2S clock fall time
8
tv(WS)
WS valid time
Master mode
4
24
th(WS)
WS hold time
Master mode
0
-
tsu(WS)
WS setup time
Slave mode
15
-
th(WS)
WS hold time
Slave mode
0
-
tsu(SD_MR) Data input setup time
Master receiver
8
-
tsu(SD_SR) Data input setup time
Slave receiver
9
-
th(SD_MR)
Data input hold time
Master receiver
5
-
th(SD_SR)
Slave receiver
4
-
tv(SD_ST) Data output valid time
Slave transmitter
(after enable edge)
-64
th(SD_ST) Data output hold time
Slave transmitter
(after enable edge)
22
-
tv(SD_MT) Data output valid time
Master transmitter
(after enable edge)
-12
th(SD_MT) Data output hold time
Master transmitter
(after enable edge)
8-
Table 52. USB: full speed electrical characteristics (continued)
Driver characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit



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