STM32F769IG datasheet(49/255 Pages) STMICROELECTRONICS

49 / 255 page

DocID029041 Rev 4

49/255

STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

Functional overview

2.42

Digital filter for Sigma-Delta Modulators (DFSDM)

The devices embed one DFSDM with 4 digital filters modules and 8 external input serial

channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM

peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to

perform digital filtering of the received data streams (which represent analog value on Σ∆

modulators inputs). The DFSDM can also interface PDM (Pulse Density Modulation)

microphones and perform PDM to PCM conversion and filtering in hardware. The DFSDM

features optional parallel data stream inputs from microcontrollers memory (through

DMA/CPU transfers into DFSDM). The DFSDM transceivers support several serial interface

formats (to support various Σ∆ modulators). The DFSDM digital filter modules perform

digital processing according user selected filter parameters with up to 24-bit final ADC

resolution.

The DFSDM peripheral supports:

•

8 multiplexed input digital serial channels:

–

Configurable SPI interface to connect various SD modulator(s)

–

Configurable Manchester coded 1 wire interface support

–

PDM (Pulse Density Modulation) microphone input support

–

Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

–

Clock output for SD modulator(s): 0..20 MHz

•

Alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):

–

internal sources: device memory data streams (DMA)

•

4 digital filter modules with adjustable digital signal processing:

–

Sincxfilter: filter order/type (1..5), oversampling ratio (up to 1..1024)

–

integrator: oversampling ratio (1..256)

•

Up to 24-bit output data resolution, signed output data format

•

Automatic data offset correction (offset stored in register by user)

•

Continuous or single conversion

•

Start-of-conversion triggered by:

–

Software trigger

–

Internal timers

–

External events

–

Start-of-conversion synchronously with first digital filter module (DFSDM0)

•

Analog watchdog feature:

–

Low value and high value data threshold registers

–

Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)

–

Input from final output data or from selected input digital serial channels

–

Continuous monitoring independently from standard conversion

•

Short circuit detector to detect saturated analog input values (bottom and top range):

–

Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream

–

Monitoring continuously each input serial channel

•

Break signal generation on analog watchdog event or on short circuit detector event

•

Extremes detector:

–

Storage of minimum and maximum values of final conversion data

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