STM32F769II datasheet(147/255 Pages) STMICROELECTRONICS

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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

Electrical characteristics

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5.3.11

PLL characteristics

The parameters given in Table 47 and Table 48 are derived from tests performed under

temperature and VDD supply voltage conditions summarized in Table 17.

Table 47. Main PLL characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPLL_IN

PLL input clock(1)

0.95(2)

2.10

MHz

fPLL_OUT

PLL multiplier output clock

216

fPLL48_OUT

48 MHz PLL multiplier output

clock

fVCO_OUT

PLL VCO output

100

432

tLOCK

PLL lock time

VCO freq = 192 MHz

200

μs

VCO freq = 432 MHz

100

300

Jitter(3)

Cycle-to-cycle jitter

System clock

216 MHz

RMS

peak

±150

Period Jitter

RMS

peak

±200

Main clock output (MCO) for

RMII Ethernet

Cycle to cycle at 50 MHz

on 1000 samples

-32

Main clock output (MCO) for MII

Ethernet

Cycle to cycle at 25 MHz

on 1000 samples

-40

Bit Time CAN jitter

Cycle to cycle at 1 MHz

on 1000 samples

330

IDD(PLL)(4)

PLL power consumption on VDD

VCO freq = 192 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLL)(4)

PLL power consumption on VDDA

VCO freq = 192 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared

between PLL and PLLI2S.

2. Guaranteed by design.

3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.

4. Guaranteed by characterization results.

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