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AD1833AAST 데이터시트(PDF) 16 Page - Analog Devices |
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AD1833AAST 데이터시트(HTML) 16 Page - Analog Devices |
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16 / 20 page ![]() REV. 0 AD1833A –16– Packed Mode 128 In Packed Mode 128, all six data channels are packed into one sample interval on one data pin. The BCLK runs at 128 fS; therefore, there are 128 BCLK periods in each sample interval. Each sample interval is broken into eight time slots: six slots of 20 BCLK and two of 4 BCLK. In this mode, the data length is restricted to a maximum of 20 bits. The three left channels are written first, MSB first, and the data is written on the falling edge of BCLK. After the three left channels are written, there is a space of four BCLK, and then the three right channels are writ- ten. The L/ RCLK defines the left and right data transmission; it is high for the three left channels and low for the three right channels. Packed Mode 256 In Packed Mode 256, all six data channels are packed into one sample interval on one data pin. The BCLK runs at 256 fS; therefore, there are 256 BCLK periods in each sample interval, and each sample interval is broken into eight time slots of 32 BCLK each. The data length can be 16, 20, or 24 bits. The three left channels are written first, MSB first, and the data is written on the falling edge of BCLK with a one BCLK period delay from the start of the slot. After the three left channels are written, there is a space of 32 BCLK, and then the three right channels are written. The L/RCLK defines the left and right data transmission; it is low for the three left channels and high for the three right channels. SLOT 1 LEFT 0 SLOT 2 LEFT 1 SLOT 3 LEFT 2 BLANK SLOT 4 SCLK SLOT 4 RIGHT 0 SLOT 5 RIGHT 1 SLOT 6 RIGHT 2 BLANK SLOT 4 SCLK DATA 20-BIT DATA 16-BIT DATA BCLK BCLK MSB –1 MSB –2 MSB –3 MSB –4 MSB –1 MSB –2 MSB –3 MSB –4 LSB +4 LSB +3 LSB +2 LSB +1 MSB LSB LSB MSB L/ RCLK Figure 11. Packed Mode 128 SLOT 1 LEFT 0 SLOT 2 LEFT 1 SLOT 3 LEFT 2 SLOT 4 RIGHT 0 SLOT 5 RIGHT 1 SLOT 6 RIGHT 2 20-BIT DATA 24-BIT DATA 16-BIT DATA BCLK MSB –1 MSB –2 MSB –3 MSB –4 MSB –1 MSB –2 MSB –3 MSB –4 LSB +8 LSB +7 LSB +6 LSB +5 LSB +4 LSB +3 LSB +2 LSB +1 LSB +4 LSB +3 LSB +2 LSB +1 MSB LSB LSB LSB MSB MSB –1 MSB –2 MSB –3 MSB –4 MSB DATA BCLK L/RCLK Figure 12. Packed Mode 256 |
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