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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TP3040AV 데이터시트(PDF) 6 Page - National Semiconductor (TI) |
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TP3040AV 데이터시트(HTML) 6 Page - National Semiconductor (TI) |
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6 / 10 page  Connection Diagrams Dual-In-Line Package TLH6660 – 3 Top View Order Number TP3040J or TP3040AJ See NS Package J16A or TP3040N or TP3040AN See NS Package N16A Plastic Lead Chip Carrier TLH6660 – 4 Order Number TP3040V or TP3040AV See NS Package V20A Description of Pin Functions Symbol Function VFxIa The non-inverting input to the transmit filter stage VFxIb The inverting input to the transmit filter stage GSx The output used for gain adjustments of the transmit filter VFRO The low power receive filter output This pin can directly drive the receive port of an electronic hy- brid PWRI The input to the receive filter differential power amplifier PWROa The non-inverting output of the receive filter pow- er amplifier This output can directly interface conventional transformer hybrids PWROb The inverting output of the receive filter power amplifier This output can be used with PWROa to differentially drive a transformer hybrid VBB The negative power supply pin Recommended input is b5V VCC The positive power supply pin The recommend- ed input is 5V VFRI The input pin for the receive filter stage Symbol Function GNDD Digital ground input pin All digital signals are ref- erenced to this pin CLK Master input clock Input frequency can be se- lected as 2048 MHz 1544 MHz or 1536 MHz PDN The input pin used to power down the TP3040 TP3040A during idle periods Logic 1 (VCC) input voltage causes a power down condition An inter- nal pull-up is provided CLK0 This input pin selects internal counters in accord- ance with the CLK input clock frequency CLK Connect CLK0 to 2048 kHz VCC 1544 kHz GNDD 1536 kHz VBB An internal pull-up is provided GNDA Analog ground input pin All analog signals are referenced to this pin Not internally connected to GNDD VFxO The output of the transmit filter stage 6 |
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