7-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS

16

MARCH 8, 2017

9DBU0741 DATASHEET

Ordering Information

“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

“A” is the device revision designator (will not correlate with the datasheet revision).

Revision History

Part / Order Number

Shipping Packaging

Package

Temperature

9DBU0741AKLF

Trays

40-pin VFQFPN

0 to +70° C

9DBU0741AKLFT

Tape and Reel

40-pin VFQFPN

0 to +70° C

9DBU0741AKILF

Trays

40-pin VFQFPN

-40 to +85° C

9DBU0741AKILFT

Tape and Reel

40-pin VFQFPN

-40 to +85° C

Rev.

Initiator Issue Date Description

Page #

A

RDW

7/15/2014 Final update and release - front page and electrical tables.

Various

B

RDW

9/19/2014

Updated SMBus Input High/Low parameters conditions, MAX values,

and footnotes.

6

C

RDW

4/14/2015

1. Updated pin out and pin descriptions to show ePad on package

connected to ground.

2. Minor updates to front page text for family consistency.

3. Updated Clock Input Parameters table to be consistent with PCIe

Vswing parameter.

1-5

D

RDW

3/8/2017

1. Updated pin 25 from VDDA1.5 to VDDO1.5 to clearly indicate that

this part has no PLL.

2. Removed "Bypass Mode" reference in "Output Duty Cycle..." and

"Phase Jitter Parameters" tables; update note 3 under Output Duty

Cycle table.

3. Changed VDDA to VDDO1.5 in Current Consumption table.

4. Updated Additive Phase Jitter conditions for PCIe Gen3.

2,3,7,8