0.026

0.65

0.03

0.65

0.015

0.375

0.098 ±0.002

2.50 ±0.05

4

5

6

1

2

3

0.026 ±0.00

0.65 ±0

0.010 ±0.005

0.25 ±0.13

0.032

0.825

4

5

6

1

3

2

Recommended Land Pattern FOR LVPECL,LVDS,HCSL

NOTE: Recommended using approximately

0.01uf bypass capacitor between PIN 6 and 3

Via to Power Layer

Via to GND

Layer

Recommended Land Pattern FOR CMOS

Via to Power Layer

Via to GND Layer

4

3

1

2

6

1

2

5

3

4

Pin

Function

1

Tri-state

2

NC

3

GND

4

Output

5

NC (CMOS) Output

(LVPECL, LVDS, HCSL)

6

Vdd

-

ASDMP

XXXXXX

XXXXXX

WEIGHT:

A3

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TITLE:

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DO NOT SCALE DRAWING

MATERIAL:

DATE

SIGNATURE

NAME

DEBUR AND

BREAK SHARP

EDGES

FINISH:

UNLESS OTHERWISE SPECIFIED:

DIMENSIONS ARE IN INCH(MM)

SURFACE FINISH:

TOLERANCES:

LINEAR:

ANGULAR:

Q.A

MFG

APPV'D

CHK'D

DRAWN

30332 Esperanza, Rancho Santa margarita, California 92688

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SMD CRYSTAL OSCILLATOR