CRYSTAL-TO-LVDS

INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER

84427 DATA SHEET

8

REVISION B 5/6/15

LVDS

All unused LVDS output pairs can be either left floating or

terminated with 100

Ω across. If they are left floating, we

recommend that there is no trace attached.

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A general interface diagram is

shown in Figure 3. The XTAL_OUT pin can be left floating. The

input edge rate can be as slow as 10ns. For LVCMOS inputs,

it is recommended that the amplitude be reduced from full

swing to half swing in order to prevent signal interference with

the power rail and to reduce noise. This configuration requires

that the output impedance of the driver (Ro) plus the series

resistance (Rs) equals the transmission line impedance. In

addition, matched termination at the crystal input will attenuate

the signal in half. This can be done in one of two ways. First, R1

and R2 in parallel should equal the transmission line impedance.

For most 50

Ω applications, R1 and R2 can be 100Ω. This can

also be accomplished by removing R1 and making R2 50

Ω.

R2

Zo = 50

VDD

Ro

Zo = Ro + Rs

R1

VDD

XTAL_IN

XTAL_OUT

.1uf

Rs