A8519KETTR-R datasheet(12/35 Pages) ALLEGRO

12 / 35 page

Wide Input Voltage Range, High-Efficiency,

Fault-Tolerant LED Driver

A8519 and

A8519-1

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Enabling the IC

The IC turns on when a logic high signal is applied on the

PWM pin with a minimum duration of tPWMH for the first clock

cycle, and the input voltage present on the VIN pin is greater

than 4.35 V to clear the UVLO threshold. Before the LEDs are

enabled, the A8519 driver goes through a system check to see

if there are any possible fault conditions that might prevent the

system from functioning correctly. Also if the FSET pin is pulled

low the IC will not power up. More information on the FSET pin

can be found in the Synchronization section of the datasheet.

FUNCTIONAL DESCRIPTION

Figure 1: Power Up Diagram Showing PWM, ISET, and VDD

Voltages and Total LED Current

Figure 2: Power Up Diagram Showing Disconnect VGATE, VLED1,

VISET, and VPWM During LED Pins Detect and Regulation Period

3.09 k

W 3.09 kW 3.09 kW

Use LED1 Channel Only

Use Four LED Channels

AGND

GND

AGND

GND

LED2

LED3

LED4

LED1

LED Strings

LED String

Figure 3: Channel Select Setup

When the voltage threshold on VLEDx pins exceeds 120 mV, a

delay between 3000 and 4000 clock cycles (1.5 to 2 ms) is used

to determine the status of the pins.

Table 1: LED Detection Duration for Given Switching Frequency

Switching Frequency

Detection Time

2 MHz

1.5 to 2 ms

1 MHz

3 to 4 ms

800 kHz

3.75 to 5 ms

600 kHz

5 to 6.7 ms

All unused LED pins should be connected with a 3.09 kΩ resis-

tor to GND. The unused pin, with the pull-down resistor, will be

taken out of regulation at this point and will not contribute to the

boost regulation loop.

VPWM

VISET

ILED(TOTAL)

VVDD

Once the IC is enabled, there are only two ways to shut down the

IC into low-power mode:

1. Pull PWM pin to low for at least 32,750 clock cycles

(approximately 16 ms at 2 MHz).

2. Cut off the supply and allow VIN to drop below UVLO fall-

ing threshold (less than 3.9 V).

Powering Up: LED Pin Check

Once VIN pin goes above UVLO and a high signal is present

on the PWM pin, the IC proceeds to power up. The A8519 then

enables the disconnect switch (GATE) and checks to see if the

LED pins are shorted to ground and/or are not used. The LED

detect phase starts when the GATE voltage of the disconnect

switch is equal to VIN – 3.3 V.

Figure 2 shows the relation of LEDx pins with respect to the

gate voltage of the disconnect switch (if used) during LED detect

phase, as well as the duration of the LED detect for a switching

frequency of 2 MHz.

VGATE

VLED1

LED current regulation begins

VPWM

LED Detection Period

GATE=Vin-3.3V

GATE voltage is pulled lower than VIN

VISET

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