OA1ZHA, OA2ZHA, OA4ZHA

Application information

DocID025994 Rev 2

21/35

5.7

Capacitive load

Driving large capacitive loads can cause stability problems. Increasing the load

capacitance produces gain peaking in the frequency response, with overshoot and ringing

in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an

op amp might become unstable.

Generally, the unity gain configuration is the worst case for stability and the ability to drive

large capacitive loads.

Figure 43: "Stability criteria with a serial resistor at VDD = 5 V" and Figure 44: "Stability

criteria with a serial resistor at VDD = 1.8 V" show the serial resistor that must be added to

the output, to make a system stable. Figure 45: "Test configuration for Riso" shows the test

Figure 43: Stability criteria with a serial resistor at VDD

= 5 V

Figure 44: Stability criteria with a serial resistor at VDD

= 1.8 V

Figure 45: Test configuration for Riso

5.8

PCB layout recommendations

Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier,

load, and power supply. The power and ground traces are critical as they must provide

adequate energy and grounding for all circuits. Good practice is to use short and wide PCB

traces to minimize voltage drops and parasitic inductance.

In addition, to minimize parasitic impedance over the entire surface, a multi-via technique

that connects the bottom and top layer ground planes together in many locations is often

used.

The copper traces that connect the output pins to the load and supply pins should be as

wide as possible to minimize trace resistance.