DocID025735 Rev 1

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STHVDAC-253M

Theory of operation

27

3.11

Settling time

The ST HVDAC will set the bias voltage of the tuner within 10µs typical after

•

Bus Park (BP) of register28 write sequence data frame if trigger mode is enabled

•

Bus Park (BP) of register 0/1/2/3 write sequence data frame if trigger mode is disabled

3.12

Operation with 1 to 3 tunable capacitors

With triggers:

It is recommended to use trigger so that outputs will be activated by write to REG_28. In

order to use the trigger, it is required to change the TRIG_MASK to 0.

When only one tunable capacitor is required it is recommended to use the REG_0

associated to OUTC.

When several tunable capacitors are required it is recommended to use extended register

write so that all DAC registers can be programmed with only one command.

The Figure 6 below represents operation when trigger and extended write are in use.

Figure 6. Operating with triggers

Table 7. Timing

OUTC unless otherwise specified

Symbol

Parameter

Condition

min

typ

(1)

1. Typical value are provided for IND = 15 µH

max unit

activation time

Activation time from shutdown to active

mode

100 300

µs

Output positive settling

time at 95%

Vout = 2 V to 20 V

equivalent load of 15 Kohms and 1 nF

10

35

µs

Output negative settling

time at 95%

Vout = 20 V to 2 V

equivalent load of 15 Kohms and 1 nF

10

35

µs

PWR_

MODE

REG_28 write(0x001C)

REG_0 write

(one tunablecapacitor)

DAC

OUTC

DAC

OUTC

DAC

OUTC

DAC

OUTC

DAC

OUTB

DAC

OUTB

DAC

OUTA

DAC

OUTA

Extended REGISTER write

(2 or 3 tunablecapacitor)

Tunable capacitor #1

(associated to OUTC)

TRIG

Initial value

Initial value

Initial value

10

µs

TRIG

Value change

Value change

Value change

10

µs

PWR_

MODE

Low Power

Initial value

Value change

Low Power

Active

100

µs

100

µs

(associated to OUTB)

(associated to OUTA)

Tunable capacitor #2

Tunable capacitor #3