STMPE812ABJR datasheet(22/53 Pages) STMICROELECTRONICS

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Interrupt system

STMPE812A

22/53

Doc ID 18225 Rev 4

INT_CTRL

Interrupt control register

Address:

0x08

Type:

R/W

Reset:

0x00

Description:

This register is used to enable the interruption from a system related interrupt source

to the host.

7654

INT_MODE

RESERVED

INT_POLARITY

INT_TYPE

GLOBAL_INT

000

[7] INT_MODE:

‘0’ for Pen-Down INT mode (INT pin asserted as long as pen down detected). Nothing can de-

assert the INT pin as long as PEN is down. TSC_TOUCH in INT_EN register must be enabled

for PEN_DOWN interrupt to operate.

If any other interrupt sources are enabled, the INT output is:

PEN_STATUS OR OTHER_INT

INT_E setting is not required for PEN-DOWN mode. It is recommended Pen-Down INT mode

enabled in applications where GPIO/ADC/PWM functions or interrupts are not in used, such

that the INT pin signal provides the exclusive indication for pen down and pen up.

‘1’ for normal INT mode (INT pin asserted if any bit in INT STATUS REGISTER is set)

When INT_MODE is changed, all interrupt status are cleared. Pending INT output (if any) is

cleared too.

[6:3] RESERVED

[2] INT_ POLARITY:

‘1’ for active high/rising edge

‘0’ for active low/falling edge

Interrupt pin should be pulled to VCC if “active low” polarity is used, and pulled to GND if “active

high” polarity is used.

[1] INT_TYPE:

‘1’ for edge interrupt (pulse width = 50-150 µs)

‘0’ for level interrupt

Edge interrupt does not work in PEN_DOWN INT mode

This bit is ignored in PEN_DOWN INT mode.

[0] GLOBAL_INT:

‘1’ allows global interrupt

‘0’ stops all interrupt

This bit overwrites INT_MODE: If global_int is stop (in pen down INT_MODE), even pen down

does not generate an interrupt.

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