STPMS2L-PUR datasheet(20/36 Pages) STMICROELECTRONICS

20 / 36 page

Theory of operation

STPMS2

20/36

DocID16525 Rev 5

Figure 16: Power supply external connection scheme

The analog part of the STPMS2 consists of:



Preamplifier in the current channel



1.23 V reference voltage generator



+3 V low drop supply voltage regulator



Two sigma-delta 2nd order modulators



BIST DAC



AGND and VREF reference buffers



Bias current generators

The voltage channel has a preamplification gain of 2, which defines the maximum

differential voltage on voltage channel inputs to ± 300 mV. The relative gain of the current

channel is selectable among 2, 4, 8 or 16, which defines the maximum differential voltage

on the current channel to ± 300 mV, ± 150 mV, ± 75 mV or ± 37.5 mV, respectively. The full

range of gains is available in soft mode only, while in hard mode 2 and 16 are the only

selectable. The temperature-compensated reference voltage generator produces VREF =

1.23 V. This generator is implemented as a bandgap generator, whose temperature

compensation curve can be selected through configuration. The low drop regulator fixes

and stabilizes the core supply voltage to VDDa = 3 V. All digital pads tolerate 5 V logic

levels. The STPMS2 is clocked by an external clock signal connected to pin CLK. The

STPMS2 sigma-delta modulators work in several operating modes, shown in Table 7:

"Operating modes" below.

Table 7: Operating modes

Operating mode

fCLK

Current consumption

LP (low power)

LPR (low precision)

1 MHZ

1.2 mA typ.

HP (fast)

HPR (high precision)

2 MHz

– 4 MHz

4 mA typ.

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