TABLE I

(Continued)

Reg

RW

Description

(in HEX)

20 – 27

Not used

3C

RW

INTERRUPT LINE

default is 0Eh

3D

R

INTERRUPT PIN

Default is 00h if HEADER pin is HIGH

Default is 01h if HEADER pin is LOW

3E – 3F

Not used

40

IDE CHANNEL 0 TIMING CONTROL REGISTER

This register is the cycle control register for 1F0h port

Default is set at B5H (Note 1)

bit 7 6

addresschip select setup time

0 0

1 PCI clk

0 1

2 PCI clk

1 0

3 PCI clk

(default)

1 1

4 PCI clk

bit543

addresschip selectwrite data hold time

0 0 0

1 PCI clk

0 0 1

2 PCI clk

0 1 0

3 PCI clk

0 1 1

4 PCI clk

1 0 0

5 PCI clk

1 0 1

6 PCI clk

1 1 0

8 PCI clk

(default)

1 1 1

12 PCI clk

bit210

Command active time

0 0 0

2 PCI clk

(Note 3)

0 0 1

3 PCI clk

0 1 0

4 PCI clk

0 1 1

5 PCI clk

1 0 0

6 PCI clk

1 0 1

8 PCI clk

(default)

1 1 0

12 PCI clk

1 1 1

16 PCI clk

41

WO

IDE CHANNEL 0 READAHEAD COUNTER LOW BYTE

It provides values for loading bit0 – bit7 of readahead counter

bit0

bit0 of the readahead counter

bit1

bit1 of the readahead counter

bit2

bit2 of the readahead counter

bit3

bit3 of the readahead counter

bit4

bit4 of the readahead counter

bit5

bit5 of the readahead counter

bit6

bit6 of the readahead counter

bit7

bit7 of the readahead counter

42

Bit 7 is

IDE CHANNEL 9 READ

AHEAD COUNTER HIGH BYTE

RW

It provides values for loading bit8 – bit9 read

ahead counter

others

bit0

bit8 of the readahead counter

are WO

bit1

bit9 of the readahead counter

bit7

readahead function control

1 enable

0 disable (default)

8