Pin Description

PCI Interface

Name

Type

Description

AD 310

IO

8 mA

MULTIPLEXED ADDRESS AND DATA

The direction of these pins are defined

below

Phase

Address Phase

input

Data Phase

Read

output

Write

input

CBE 30

I

COMMANDBYTE ENABLE

are multiplexed Bus command and Byte enables

PAR

IO

8 mA

PARITY

is even parity across AD 310 and CBE 30 PAR is an input during

writes and an output during reads

FRAME

I

CYCLE FRAME

is driven by the initiator to indicate the beginning and duration of

an access

TRDY

OTRI-STATE

12 mA

TARGET READY

indicates that the current data phase of the transaction is ready

to be completed

IRDY

I

INITIATOR READY

indicates that the initiator is ready to complete the current

data phase of the transaction

STOP

OTRI-STATE

8 mA

STOP

indicates that the current target is requesting the initiator to stop the current

transaction

DEVSEL

OTRI-STATE

8 mA

DEVICE SELECT

when actively drive indicates the driving device has decoded

its adderss as the target of the current access

IDSEL

I

INITIALIZATION DEVICE SELECT

is used as a chip select during configuration

read and write transactions

PERR

OTRI-STATE

8 mA

PARITY ERROR

is used for reporting data parity errors during all PCI transactions

except a Special Cycle PERR

is an output during writes and an input during

reads

SERR

OTRI-STATE

8 mA

SYSTEM ERROR

is used for reporting address parity errors data parity errors on

the Special Cycle command or any other system error where the result will be

castrophic When reporting address parity errors SERR

is an output When

reporting data parity errors for the Special Cycle command SERR

is an output

during writes and an input during needs

INTA

B

OTRI-STATE

8 mA Slew

INTERRUPT

Interrupt request A and B

Rate Control

CLK

I

CLOCK

Up to 33 MHz PCI Clock

RST

I

RESET

PCI Reset

Power and Ground

Name

Type

Description

GND

I

I

Note

All signals are TTL except CH0

INT (Pin 48) and CH1

INT (Pin 87) are CMOS

5