TP112

4

TP112-DS-P02

Jan 5, 2000

PIN Description (continued)

PIN NO.

LABEL

TYPE

DESCRIPTION

Modes

36

MDC

I

Management Data Clock

MII management data clock input, maximum clock rate is

2.5MHz

37

MDIO

I/O

Management Data I/O

MII management data input/output

19

TMODE

I

Test Mode

Active high. Set TP112 into test mode, and low for normal

operation. There’s an internal pull low resistor so default is

normal operation

18

HALFONLY

I/IPL

Half Duplex Mode Only

1: half duplex

0: full duplex

15

FORCEON

I/IPL

Force Mode Enable

1: force mode enable

0: auto negotiation mode enable

LEDs

69

FDXLED*

O

Full Duplex LED

Before link OK, this pin is tri-stated. After link OK this pin

indicate current duplex operation for TP112. High for half

duplex and low for full duplex

78

28

LRLED*

FXLRLED*

O

Link/Receive LED

Active low. Indicates the link status of the port, driven low

when link to the port is good. Output for 20mS clock while the

TP112 is receiving data from external media

79

27

TXLED*

FXTLED*

O

Transmit LED

Active low. Indicates that data is being transmitting

Reset & Clock

80

RESET*

I

Reset

Active low. Reset TP112, remain low at least 1us.

91

OSCI/X1

I

Oscillator input or crystal input

(25MHz±50ppm).

90

X2

O

Crystal output. Leave it unconnected (i.e., as a NC pin) when

oscillator is used.

Current Reference

10

BGRES

I

Band Gap Resistor

A 6.2KOhm 1% resistor that supply 200uA reference current

for receive

11

BGGND

I

Band Gap Resistor Ground

Band gap resistor ground reference input