AD9261 datasheet(9/29 Pages) AD

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AD9261

Rev. 0 | Page 8 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK–

CVDD

PDWN

DVDD

DGND

DRVDD

PLL_LOCKED

DCO

NOTES

1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR

THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB

INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING

THE THERMAL CAPACITY OF THE PACKAGE.

PLLMULT1/SDIO

PLLMULT2

PLLMULT3

PLLMULT4

DVDD

DGND

DRVDD

D15

D14

D13

PLLMULT0/SCLK

AD9261

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

Figure 3. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

CLK−

Clock Input (−).

CVDD

Clock Supply (1.8 V).

PDWN

External Power-Down Pin.

4, 19, 31

DVDD

Digital Supply (1.8 V).

5, 18, 30

DGND

Digital Ground.

6, 17, 29

DRVDD

Digital Output Driver Supply (1.8 V to 3.3 V).

PLL_LOCKED

PLL Lock Indicator.

DCO

Data Clock Output.

9 to 16, 20 to 27

D0 to D15

Data Output Bits. D0 is the LSB and D15 is the MSB.

Overrange Indicator.

32, 33, 34

PLLMULT4, PLLMULT3, PLLMULT2

PLL Mode Selection Pins.

PLLMULT1/SDIO

PLL Mode Selection Pin/Serial Port Interface Data Input/Output.

PLLMULT0/SCLK

PLL Mode Selection Pin/Serial Port Interface Clock.

CSB

Serial Port Interface Chip Select. Active low.

38, 46

AGND

Analog Ground.

39, 42, 45

AVDD

Analog Supply (1.8 V).

VREF

Voltage Reference Input/Output.

CFILT

Noise Limiting Filter Capacitor.

VIN+

Analog Input (+).

VIN–

Analog Input (−).

CGND

Clock Ground.

CLK+

Clock Input (+).

EPAD

Analog Ground. Pin 49 is the exposed thermal pad on the bottom of the package.

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