AM79C875KC datasheet(33/48 Pages) AMD

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Am79C875

Receive Error Counter (Register 21)

Table 21. Receive Error Counter (Register 21)

Reg

Bit

Name

Description

Read/

Write

Default

15:0

RX_ER Counter

Count of Receive Error Events.

0000 (hex)

Mode Control Register (Register 24)

Table 22. Mode Control Register (Register 24)

Reg

Bit

Name

Description

Read/

Write

Default

SDCM_SEL

Select Common Mode Voltage Setting for FX Signal Detect (SDI)

input signal.

1 = Select Internal Common Mode Setting.

0 = Select External Common Voltage Setting.

Force 10BASE-T

Link Up

1 = Force link up at 10 Mbps without checking NLP. Auto-

Negotiation must be disabled and the data rate must be 10 Mbps.

0 = Normal Operation.

Force

100BASE-TX

Link Up

1 = Force link up at 100 Mbps. Auto-Negotiation must be disabled

and the data rate must be 100 Mbps.

0 = Normal Operation.

Jabber Disable

1 = Disable Jabber function in PHY.

0 = Enable Jabber function in PHY.

Reserved

Write as 0, ignore when read.

Activity LED

Configuration

1 = Activity only responds to receive operation.

0 = Activity responds to Receive and transmit.

In repeater mode, this bit will be ignored.

Reserved

Write as 0, ignore when read.

FEFI_Disable

Set this bit will disable FEFI generation and detection function. The

default value of this bit is 0 when the chip is working in FX mode.

Otherwise the default value is 1.

Set by

FX_DIS and

ANEGA pins

Force FEFI

Transmit

This bit is set to force the transmit FEFI pattern.

RX_ER_CNT Full This bit is set to one to indicate the Receive Error Counter is full.

RO/RC

Disable

RX_ER counter

1 = disable Receive Error Counter.

DIS_WDT

1 = Disable the watchdog timer in the decipher.

EN_RPBK

1 = Enable remote loopback, 0 = Disable remote loopback.

EN_SCRM

0 = Disable data scrambling.

1 = Enable data scrambling.

When FX_DIS pin is asserted low or FX_SEL bit (Register 24.0) is

set to logic high, this bit will be overwritten as “1” automatically.

The default of this bit is set by power on read value of FX_DIS.

Set by

SCRAM_EN

Reserved

Write as 0, ignore when read.

FX_SEL

Set this bit to logic 1 to select 100BASE-FX mode, set to logic 0 to

select 100BASE-TX.

Set by

FX_DIS

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