TSV63X datasheet(8/31 Pages) STMICROELECTRONICS

8 / 31 page

Electrical characteristics

TSV632, TSV632A, TSV633, TSV633A, TSV634,

TSV634A, TSV635, TSV635A

8/31

DocID15688 Rev 6

Table 6: VCC+ = 3.3 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, RL connected to VCC/2

(unless otherwise specified)

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

DC performance

Vio

Offset voltage

TSV63x

TSV63xA

0.8

TSV633AIST (MiniSO10)

Tmin < Top < Tmax - TSV63x

4.5

Tmin < Top < Tmax - TSV63xA

Tmin < Top < Tmax - TSV633AIST

2.2

∆Vio/∆T

Input offset voltage drift

μV/°C

Iio

Input offset current

Vout = VCC/2

(1)

Tmin < Top < Tmax

100

Iib

Input bias current

Vout = VCC/2

(1)

Tmin < Top < Tmax

100

CMR

Common mode rejection

ratio 20 log (ΔVic/ΔVio)

0 V to 3.3 V, Vout = 1.65 V

Tmin < Top < Tmax

Avd

Large signal voltage gain

RL = 10 kΩ, Vout = 0.5 V to 2.8 V

Tmin < Top < Tmax

VOH

High level output voltage,

(VOH = VCC - Vout)

RL = 10 kΩ

Tmin < Top < Tmax

VOL

Low level output voltage

RL = 10 kΩ

Tmin < Top < Tmax

Iout

Isink

Vo = 3.3 V

Tmin < Top < Tmax

Isource

Vo = 0 V

Tmin < Top < Tmax

ICC

Supply current,

(per channel)

No load, Vout = 1.75 V

µA

Tmin < Top < Tmax

AC performance

GBP

Gain bandwidth product

RL = 2 kΩ, CL = 100 pF,

f = 100 kHz

710

860

kHz

ɸm

Phase margin

RL = 2 kΩ, CL = 100 pF

Degrees

Gain margin

RL = 2 kΩ, CL = 100 pF

Slew rate

RL = 2 kΩ, CL = 100 pF, AV = 1

0.22

0.29

V/μs

Notes:

(1)

Guaranteed by design

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