S128 datasheet(49/107 Pages) RENESAS

49 / 107 page

R01DS0309EU0100 Rev.1.00

Page 49 of 107

Mar 10, 2017

S128

2. Electrical Characteristics

2.3

AC Characteristics

2.3.1

Frequency

Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for

programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.

A non-integer frequency such as 1.5 MHz cannot be set.

Note 2. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the

frequency accuracy of the clock source.

Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D

converter is in use.

Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,

PCLKB, and PCLKD.

Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of

guaranteed operation, see Table 2.21, Clock timing.

Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for

programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.

A non-integer frequency such as 1.5 MHz cannot be set.

Note 2. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the

frequency accuracy of the clock source.

Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D

converter is in use.

Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,

PCLKB, and PCLKD.

Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of

guaranteed operation, see Table 2.21, Clock timing.

Table 2.16

Operation frequency in high-speed operating mode

Conditions: VCC = AVCC0 = 2.4 to 5.5 V

Parameter

Symbol

Min

Typ

Max*5

Unit

Operation

frequency

System clock (ICLK)*1, *2, *4

2.7 to 5.5 V

0.032768

MHz

2.4 to 2.7 V

0.032768

Peripheral module clock (PCLKB)*4

2.7 to 5.5 V

2.4 to 2.7 V

Peripheral module clock (PCLKD)*3,

2.7 to 5.5 V

2.4 to 2.7 V

Table 2.17

Operation frequency in middle-speed mode

Conditions: VCC = AVCC0 = 1.8 to 5.5 V

Parameter

Symbol

Min

Typ

Max*5

Unit

Operation

frequency

System clock (ICLK)*1, *2, *4

2.7 to 5.5 V

0.032768

MHz

2.4 to 2.7 V

0.032768

1.8 to 2.4 V

0.032768

Peripheral module clock (PCLKB)*4

2.7 to 5.5 V

2.4 to 2.7 V

1.8 to 2.4 V

Peripheral module clock (PCLKD)*3, *4

2.7 to 5.5 V

2.4 to 2.7 V

1.8 to 2.4 V

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