 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
S3A3 데이터시트(PDF) 127 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
S3A3 데이터시트(HTML) 127 Page - Renesas Technology Corp |
|
|
127 / 139 page  R01DS0307EU0100 Rev.1.00 Page 127 of 139 Mar 7, 2017 S3A3 2. Electrical Characteristics 2.17.1 Serial Wire Debug (SWD) Figure 2.98 SWD SWCLK timing Table 2.84 SWD characteristics (1) Conditions: VCC = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 80 - - ns Figure 2.98 SWCLK clock high pulse width tSWCKH 35 - - ns SWCLK clock low pulse width tSWCKL 35 - - ns SWCLK clock rise time tSWCKr -- 5 ns SWCLK clock fall time tSWCKf -- 5 ns SWDIO setup time tSWDS 16 - - ns Figure 2.99 SWDIO hold time tSWDH 16 - - ns SWDIO data delay time tSWDD 2 - 70 ns Table 2.85 SWD characteristics (2) Conditions: VCC = 1.6 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 250 - - ns Figure 2.98 SWCLK clock high pulse width tSWCKH 120 - - ns SWCLK clock low pulse width tSWCKL 120 - - ns SWCLK clock rise time tSWCKr -- 5 ns SWCLK clock fall time tSWCKf -- 5 ns SWDIO setup time tSWDS 50 - - ns Figure 2.99 SWDIO hold time tSWDH 50 - - ns SWDIO data delay time tSWDD 2 - 150 ns SWCLK tSWCKcyc tSWCKH tSWCKf tSWCKr tSWCKL |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
