PS9352AL2 datasheet(5/21 Pages) RENESAS

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PS9352AL2

Chapter Title

R08DS0129EJ0100 Rev.1.00

Page 5 of 19

Aug 24, 2015

ELECTRICAL CHARACTERISTICS

(TYP.: TA = 25

C, VIN = VIN = 0 V, VDD1 = VDD2 = 5 V,

MIN., MAX.: refer to RECOMMENDED OPERATING CONDITIONS, unless otherwise specified)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input Supply Current

IDD1

VIN = 350 mV

12.6

Output Supply Current

IDD2

VIN =

350 mV

Input Bias Current

IIN

5

0.6

A

Low Level Saturated Output Voltage

VOL

IOUT = 1.6 mA

0.1

0.6

High Level Saturated Output Voltage

VOH

IOUT =

100

A

3.9

4.9

Output Short-circuit Current

|IOSC|

VOUT = VDD2 or VOUT = GND2

Equivalent Input Resistance

RIN

450



Output Clock Frequency

fCLK

8.2

13.2

MHz

Isolation Resistance

RI-O

VI-O = 1 kVDC, TA = 25

C

1011



Isolation Capacitance

CI-O

f = 1 MHz

0.7

Data Hold Time *1

tHDDAT

Common Mode Transient Immunity *2

CMR

VCM = 1 kV, TA = 25

C

kV/

s

The data hold time (tHDDAT) is that the data (MDAT) will stay stable following the rising edge of the clock (MCLK).

tHDDAT is shown in the below timing chart.

Fig. Timing Chart

Common Mode Transient Immunity (CMR) is specified by the rate of rise / fall of a pulse applied between GND1

on the input side and GND2 on the output side (pins 4 and 5) by using the circuit shown in Fig. 6 CMR Test

Circuit

. CMR is defined at the point that clock signals are corrupted.

MCLK

MDAT

tHDDAT

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