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WM9710 데이터시트(PDF) 12 Page - Wolfson Microelectronics plc |
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WM9710 데이터시트(HTML) 12 Page - Wolfson Microelectronics plc |
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12 / 32 page ![]() WM9710 Production Data w PD Rev 4.0 December 2003 12 WARM RESET SYNC BITCLK t SYNC_HIGH t SYNC2CLK Figure 6 Warm Reset Timing PARAMETER SYMBOL MIN TYP MAX UNIT SYNC active high pulse width tSYNC_HIGH 1.3 µs SYNC inactive to BITCLK startup delay tSYNC2CLK 162.4 ns CLOCK SPECIFICATIONS BITCLK SYNC t CLK_HIGH t CLK_LOW t CLK_PERIOD t SYNC_HIGH t SYNC_LOW t SYNC_PERIOD Figure 7 Clock Specifications (50pF External Load) PARAMETER SYMBOL MIN TYP MAX UNIT BITCLK frequency 12.288 MHz BITCLK period tCLK_PERIOD 81.4 ns BITCLK output jitter 750 ps BITCLK high pulse width (Note 1) tCLK_HIGH 36 40.7 45 ns BITCLK low pulse width (Note 1) tCLK_LOW 36 40.7 45 ns SYNC frequency 48.0 kHz SYNC period tSYNC_PERIOD 20.8 µs SYNC high pulse width tSYNC_HIGH 1.3 µs SYNC low pulse width tSYNC_LOW 19.5 µs Note: Worst case duty cycle restricted to 45/55. |
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