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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HT48R002 데이터시트(PDF) 39 Page - Holtek Semiconductor Inc |
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HT48R002 데이터시트(HTML) 39 Page - Holtek Semiconductor Inc |
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39 / 71 page  Rev. 1.11 38 April 11, 2017 Rev. 1.11 39 April 11, 2017 HT48R002/HT48R003 Cost-Effective I/O 8-Bit OTP MCU HT48R002/HT48R003 Cost-Effective I/O 8-Bit OTP MCU Timer Register – TMR0 ThetimerregisterisspecialfunctionregisterlocatedintheSpecialPurposeDataMemoryandisthe placewheretheactualtimervalueisstored.TheregisterisknownasTMR0.Thevalueinthetimer registerincreasesbyoneeachtimeaninternalclockpulseisreceivedoranexternaltransitionoccurs ontheexternaltimerpin.Thetimerwillcountfromtheinitialvalueloadedbythepreloadregisterto thefullcountofFFHatwhichpointthetimeroverflowsandaninternalinterruptsignalisgenerated. Thetimervaluewillthenresetwiththeinitialpreloadregistervalueandcontinuecounting. NotethattoachieveamaximumfullrangecountofFFH,thepreloadregistermustfirstbecleared. Itshouldbenotedthatafterpower-on,thepreloadregisterwillbeinanunknowncondition.Note thatiftheTimer/EventCounterisinanOFFconditionanddataiswrittentoitspreloadregister, thisdatawillbeimmediatelywrittenintotheactualcounter.However,ifthecounterisenabledand counting,anynewdatawrittenintothepreloaddataregisterduringthisperiodwillremaininthe preloadregisterandwillonlybewrittenintotheactualcounterthenexttimeanoverflowoccurs. Timer Control Register – TMR0C TheflexiblefeaturesoftheHoltekmicrocontrollerTimer/EventCounterenableittooperateinthree differentmodes,theoptionsofwhicharedeterminedbythecontentsoftheirrespectivecontrol register. TheTimerControlRegisterisknownasTMR0C.ItistheTimerControlRegistertogetherwith itscorrespondingtimerregisterthatcontrolsthefulloperationoftheTimer/EventCounter.Before thetimercanbeused,itisessentialthattheTimerControlRegisterisfullyprogrammedwiththe rightdatatoensureitscorrectoperation,aprocessthatisnormallycarriedoutduringprogram initialization. Tochoosewhichofthethreemodesthetimeristooperatein,eitherinthetimermode,theevent countingmodeorthepulsewidthcapturemode,bits7and6oftheTimerControlRegister,which areknownasthebitpairT0M1/T0M0,mustbesettotherequiredlogiclevels.Thetimer-onbit, whichisbit4oftheTimerControlRegisterandknownasT0ON,providesthebasicon/offcontrol oftherespectivetimer.Settingthebittohighallowsthecountertorun.Clearingthebitstopsthe counter.Bits0~2oftheTimerControlRegisterdeterminethedivisionratiooftheinputclock prescaler.Theprescalerbitsettingshavenoeffectifanexternalclocksourceisused.Ifthetimeris intheeventcountorpulsewidthcapturemode,theactivetransitionedgeleveltypeisselectedby thelogiclevelofbit3oftheTimerControlRegisterwhichisknownasT0EG. |
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