W78ERD2 datasheet(21/76 Pages) ETC2

21 / 76 page

W78ERD2/W78ERD2A

Publication Release Date: March 2, 2009

- 21 -

Revision A12

BIT

NAME

FUNCTION

7, 6

P43FUN1

P43FUN0

00: Mode 0. P4.3 is a general purpose I/O port, like Port 1.

01: Mode 1. P4.3 is a read-strobe signal for chip-select purposes. The

address range depends on SFR P43AH, P43AL, P43CMP1 and

P43CMP0.

10: Mode 2. P4.3 is a write-strobe signal for chip-select purposes. The

address range depends on SFR P43AH, P43AL, P43CMP1 and

P43CMP0.

11: Mode 3. P4.3 is a read/write-strobe signal for chip-select purposes. The

address range depends on SFR P43AH, P43AL, P43CMP1, and

P43CMP0.

5, 4

P43CMP1

P43CMP0

Chip-select signal address comparison:

00: Compare the full 16-bit address with P43AH and P43AL.

01: Compare the 15 MSB of the 16-bit address with P43AH and P43AL.

10: Compare the 14 MSB of the 16-bit address with P43AH and P43AL.

11: Compare the 8 MSB of the 16-bit address with P43AH.

3, 2

P42FUN1

P42FUN0

P4.2 function control bits, similar to P43FUN1 and P43FUN0 above.

1, 0

P42CMP1

P42CMP0

P4.2 address-comparator length control bits, similar to P43CMP1 and

P43CMP0 above.

F/W Flash Low Address

Bit:

Mnemonic: SFRAL

Address: C4h

F/W flash low byte address

F/W Flash High Address

Bit:

Mnemonic: SFRAH

Address: C5h

F/W flash high byte address

F/W Flash Data

Bit:

Mnemonic: SFRFD

Address: C6h

F/W flash data

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