USB97CFDC-MN datasheet(14/20 Pages) SMSC

14 / 20 page

SMSC DS – USB97CFDC

Page 14

Rev. 12/15/2000

FIGURE 4 - SRAM MEMORY READ TIMING

Table 5 – SRAM Memory Read Timing

NAME

PARAMETER

MIN

TYP

MAX

UNITS

SA[19:0] valid before nMEMRD asserted

nMEMRD pulse width

100

SD[7:0] Data setup time to nMEMRD de-asserted

SD[7:0] Data hold time from nMEMRD de-asserted

nMEMRD de-asserted to SA [13:0] invalid

FIGURE 5 - DISK DRIVE TIMING

SA [1 3 :0

S D [7 :0 ]

nM E M R

TYP

nDIR

nSTEP

nDS0

nINDEX

nRDATA

nWDATA

*X specifies one MCLK period and Y specifies one WCLK period.

MCLK = 16x Data Rate (at 500 Kbp/s MCLK = 8 MHz)

WCLK = 2x Data Rate (at 500 Kbp/s WCLK = 1 MHz)

PARAMETER

MIN

MAX

UNITS

nDIR Set Up to nSTEP Low

nSTEP Active Time Low

nDIR Hold Time After nSTEP

nSTEP Cycle Time

nDS0-1 Hold Time from nSTEP Low

nINDEX Pulse Width

nRDATA Active Time Low

nWDATA Write Data Width Low

132

NAME

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