CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

DS752F1

17

Figure 7. Parallel Control Port - Intel



Slave Mode Read Cycle

Delay between PCP_RD then PCP_CS low or PCP_CS then

PCP_RD low

0—

—

ns

Data valid after PCP_CS and PCP_RD low

——

18

ns

PCP_CS and PCP_RD low for read

24

—

—

ns

Data hold time after PCP_CS or PCP_RD high

8—

—

ns

Data high-Z after PCP_CS or PCP_RD high

——

18

ns

PCP_CS or PCP_RD high to PCP_CS and PCP_RD low for next

30

—

—

ns

PCP_CS or PCP_RD high to PCP_CS and PCP_WR low for next

write1

30

—

—

ns

PCP_RD rising to PCP_IRQ rising

——

12

ns

Write

Delay between PCP_WR then PCP_CS low or PCP_CS then

PCP_WR low

0—

—

ns

Data setup before PCP_CS or PCP_WR high

8—

—

ns

PCP_CS and PCP_WR low for write

24

—

—

ns

Data hold after PCP_CS or PCP_WR high

8—

—

ns

PCP_CS or PCP_WR high to PCP_CS and PCP_RD low for next

read1

30

—

—

ns

PCP_CS or PCP_WR high to PCP_CS and PCP_WR low for next

write1

30

—

—

ns

PCP_WR rising to PCP_BSY falling

—

2*DCLKP + 20

—

ns

1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware

application. Hardware handshaking on the PCP_

CS4953x4/CS4970x4 System Designer’s Guide should be consulted for the firmware speed limitations.

Parameter

Symbol Min

Typical

Max

Unit

PCP_A[3:0]

PCP_D[7:0]

PCP_CS#

PCP_WR#

PCP_RD#

PCP_IRQ#

LSP

MSP