WM8233 datasheet(11/146 Pages) CIRRUS

11 / 146 page

WM8233

Rev 4.7

INTERNAL POWER ON RESET CIRCUIT

Power On Reset

Circuit

AVDD

INTERNAL PORB

VDD

GND

AGND

LDOOUT

Figure 1 Internal Power On Reset Circuit Schematic

The WM8233 includes an internal Power-On-Reset Circuit, as shown in Figure 1, which is used reset

the digital logic into a default state after power up. The POR circuit is powered from AVDD and

monitors LDOOUT. It asserts PORB low if AVDD or LDOOUT is below a minimum threshold.

LDOOUT

AVDD

Vpord_on

LDOGND

AGND

Internal POR active

Device Ready

Internal

POR active

No Power

POR

Undefined

Vpora_off

Vpora

INTERNAL PORB

Figure 2 Typical Power up Sequence where AVDD is Powered before LDOOUT

Figure 2 shows a typical power-up sequence where AVDD is powered up first. When AVDD rises

above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is

asserted low and the chip is held in reset. In this condition, all writes to the control interface are

ignored. When LDOOUT rises to Vpord_on, PORB is released high and all registers are in their

default state and writes to the control interface may take place. On power down, where AVDD falls

first, PORB is asserted low whenever AVDD drops below the minimum threshold Vpora_off.

SYMBOL

MIN

TYP

MAX

UNIT

Vpora

0.4

0.6

0.8

Vpora_off

0.4

0.6

0.8

Vpord_on

0.5

0.7

0.9

Table 1 Typical POR Operation (typical values, not tested)

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