TMS320DM6431 datasheet(76/227 Pages) TI1

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3.6.1

Switch Central Resource (SCR) Bus Priorities

TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

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Prioritization within the Switched Central Resource (SCR) is programmable for each master. The register

bit fields and default priority levels for DM6431 bus masters are shown in Table 3-13, DM6431 Default Bus

Master Priorities. The priority levels should be tuned to obtain the best system performance for a particular

application. Lower values indicate higher priority. For most masters, their priority values are programmed

at the system level by configuring the MSTPRI0 and MSTPRI1 registers. Details on the MSTPRI0/1

registers are shown in Figure 3-6 and Figure 3-7. The C64x+, VPSS, and EDMA masters contain registers

that control their own priority values.

Table 3-13. DM6431 Default Bus Master Priorities

Priority Bit Field

Bus Master

Default Priority Level

VPSSP

VPSS

0 (VPSS PCR Register)

EDMATC0P

EDMATC0

0 (EDMACC QUEPRI Register)

EDMATC1P

EDMATC1

0 (EDMACC QUEPRI Register)

EDMATC2P

EDMATC2

0 (EDMACC QUEPRI Register)

C64X+_DMAP

C64X+ (DMA)

7 (C64x + MDMAARBE.PRI field)

C64X+_CFGP

C64X+ (CFG)

1 (MSTPRI0 Register)

EMACP

EMAC

4 (MSTPRI1 Register)

RESERVED

R-0000 0000 0000 0000

RESERVED

C64X+_CFGP

RESERVED

R-0000 0

R/W-001

R-0000 0000

LEGEND: R = Read; W = Write; -n = value after reset

Figure 3-6. MSTPRI0 Register— 0x01C4 003C

Table 3-14. MSTPRI0 Register Description

Bit

Field Name

Description

31:11

RESERVED

Reserved. Read-only, writes have no effect.

C64X+_CFG master port priority in System Infrastructure.

000 = Priority 0 (Highest)

100 = Priority 4

10:8

C64X+_CFGP

001 = Priority 1

101 = Priority 5

010 = Priority 2

110 = Priority 6

011 = Priority 3

111 = Priority 7 (Lowest)

7:0

RESERVED

Reserved. Read-only, writes have no effect.

Device Configurations

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