| 전자부품 데이터시트 검색엔진 |
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LP3997 데이터시트(PDF) 2 Page - National Semiconductor (TI) |
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LP3997 데이터시트(HTML) 2 Page - National Semiconductor (TI) |
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2 / 11 page ![]() Functional Block Diagram 20092908 Pin Descriptions Pin # Name Description 1 CNOISE Noise bypass pin. For low noise applications a 0.1µF or larger ceramic capacitor should be connected from this pin to ground 2 DELAY A capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the ERROR (pin 7) output. 3 GND Ground pin. Local ground for C NOISE and COUT. 4V IN Input supply pin. Bypass this with a 1µF capacitor. 5V OUT Output voltage, Connect C OUT between this pin and ground. 6 SENSE Connect this pin to VOUT (pin 5). 7 ERROR This open drain output is an error flag output which goes low when V OUT drops 5% below it nominal voltage. This pin also provides a power-on-reset signal if a capacitor is connected to the DELAY pin. 8SD Shutdown. Disables the regulator when less than 0.4V is applied. Enables the regulator when greater than 0.9V. The Shutdown pin is pulled down internally bya6M Ω resistor. Connection Diagram 8 Lead MSOP NS Package Number MUA08A 20092904 www.national.com 2 |
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