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PC33981PNA/R2 데이터시트(PDF) 9 Page - Motorola, Inc

부품명 PC33981PNA/R2
상세설명  High-Frequency, High-Current, Self-Protected High-Side Switch (4.0 m??up to 60 kHz)
PDF  24 Pages
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제조업체  MOTOROLA [Motorola, Inc]
홈페이지  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

PC33981PNA/R2 데이터시트(HTML) 9 Page - Motorola, Inc

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33981
9
Table 1. Functional Truth Table in Normal Mode
Condition
CONF INHS
INLS
OUT
GLS
FS
EN
Comments
Sleep
x
x
x
x
x
H
L
Device is in Sleep mode. The OUT and
low-side gate are OFF.
Normal
L
H
H
H
H
H
H
Normal mode. High side and low side are
controlled independently. The high side
and the low side are both on.
Normal
L
L
L
L
L
H
H
Normal mode. High side and low side are
controlled independently. The high side
and the low side are both off.
Normal
H
L
H
L
H
H
H
Normal mode. No cross-conduction. Half-
bridge configuration. The high side is off
and the low side is on.
Normal
H
H
L
H
L
H
H
Normal mode. No cross-conduction. Half-
bridge configuration. The high side is on
and the low side is off.
Normal
H
PWM
H
PWM
PWM
OR H
(Logical
OR)
H
H
Normal mode. Cross-conduction
management is activated. Half-bridge
configuration.
H = High level
L = Low level
x = Don’t care
PWM = Pulse-width modulation
Table 2. Functional Truth Table in Fault Mode
Conditions
CONF INHS
INLS
OUT
GLS
FS
EN
TEMP CSNS OCLS
Comments
Overtemperature
on OUT
x
x
x
L
x
L
H
L
x
x
The 33981 is currently in fault mode. The
OUT is OFF. TEMP at 0 V indicates this
fault. Once the fault is removed 33981
recovers its normal mode.
Overtemperature
on CBOOT or GLS
x
x
x
L
L
L
H
L
x
x
The 33981 is currently in fault mode. The
OUT is OFF and GLS is at 0 V. TEMP at
0 V indicates this fault. Once the fault is
removed 33981 recovers its normal mode.
Overcurrent
on OUT
x
H
x
L
x
L
H
x
L
x
The 33981 is currently in fault mode. The
OUT is OFF. It is reset by a logic [0] at
INHS for at least 200
µs. When INHS goes
to 0 V, CSNS goes to 5.0 V.
Overload
on External Low-
Side MOSFET
L
x
H
x
L
L
H
x
x
L
The 33981 is currently in fault mode. GLS
is at 0 V and OCLS internal current source
is off. The external resistance connected
between OCLS and GND terminal will pull
OCLS terminal to 0 V. The fault is reset by
a logic [0] at INLS for at least 200
µs.
H = High level
L = Low level
x = Don’t care
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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