전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

ADCS9888 데이터시트(PDF) 29 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 ADCS9888
상세설명  205/170/140 MSPS Video Analog Front End
PDF  34 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADCS9888 데이터시트(HTML) 29 Page - National Semiconductor (TI)

Back Button ADCS9888 Datasheet HTML 25Page - National Semiconductor (TI) ADCS9888 Datasheet HTML 26Page - National Semiconductor (TI) ADCS9888 Datasheet HTML 27Page - National Semiconductor (TI) ADCS9888 Datasheet HTML 28Page - National Semiconductor (TI) ADCS9888 Datasheet HTML 29Page - National Semiconductor (TI) ADCS9888 Datasheet HTML 30Page - National Semiconductor (TI) ADCS9888 Datasheet HTML 31Page - National Semiconductor (TI) ADCS9888 Datasheet HTML 32Page - National Semiconductor (TI) ADCS9888 Datasheet HTML 33Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 29 / 34 page
background image
Application Information (Continued)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A6
A5
A4
A3
A2
A1
A0
R/W
100110
A0
Pin
0
6.2.5 Register Address BYTE
ADCS9888 register addresses are an 8 bit value. Please
refer to the Register Address table at the beginning of the
datasheet for more detailed information.
6.2.6 Serial Interface Timeout
The serial interface incorporates a timeout feature. This is
present to ensure that the bus cannot become ‘locked’ if the
master and slave become out of sync due to noise or other
system issues.
An internal timer is used to guarantee that the interface is
reset if the SCL line is held low. This is used to prevent
problems in the case where the ADCS9888 is driving a low
on the SDA line and the master device is reset. This allows
the master to reset the state of the serial interface on the
ADCS9888 by simply driving a low on SCL for more than 50
ms.
The serial bus interface circuitry will be reset to the idle state
if the SCL line is held low for more than 50 ms. The bus may
be reset to idle if the SCL line is held low from 25 to 50 ms.
The bus will not be reset if the SCL line is held low for less
than 25 ms.
6.3 Specific Types Of Transfers
6.3.1 Write to Single Register
•
Start Signal
•
Slave Address Byte (R/W Bit = 0)
•
Register Address Byte
•
Data Byte to Register
•
Stop Signal
6.3.2 Burst Write to Multiple (3) Registers
•
Start Signal
•
Slave Address Byte (R/W Bit = 0)
•
Register Address Byte
•
Data Byte to Register
•
Data Byte to Register+1
•
Data Byte to Register+2
•
Stop Signal
6.3.3 Read from Single Register
•
Start Signal
•
Slave Address Byte (R/W Bit = 0)
•
Register Address Byte
•
Start Signal
•
Slave Address Byte (R/W Bit = 1)
•
Data Byte to Register
•
Stop Signal
6.3.4 Read from Multiple (3) Registers
•
Start Signal
•
Slave Address Byte (R/W Bit = 0)
•
Register Address Byte
•
Start Signal
•
Slave Address Byte (R/W Bit = 1)
•
Data Byte to Register
•
Data Byte to Register+1
•
Data Byte to Register+2
•
Stop Signal
www.national.com
29



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com